Technology mapping for high-performance static CMOS and pass transistor logic designs

Two new techniques for mapping circuits are proposed in this paper. The rst method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS/PTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, and utilizes the relation between PTL and binary decision diagrams. The methods are very e cient and can handle all of the ISCAS'85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on di erent libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the Static CMOS/PTL method, with signi cant savings in the area.